tinyML Summit 2021

Enabling ultra-low Power Machine Learning at the Edge

March 22-26, 2021

About

The tinyML Summit will be held virtually the week of March 22, 2021. We are in the process of re-envisioning our flagship event as a highly interactive online experience.

In conjunction with the Summit, we are also pleased to announce that we have added a new event for 2021: the tinyML Research Symposium.

The tinyML Summit is the premier annual gatherings of senior level technical experts and decision makers representing fast growing global tinyML community. This diverse ecosystem is composed of professionals from industry, academia, start-ups, and government labs worldwide working on leading-edge ultra-low power machine learning technologies for end-to-end (hardware –system –software applications full stack) solutions.

Venue

Virtual - online

Contact us

Bette COOPER

News

  • February 12, 2021

    tinyML Summit 2021 Breakout Sessions

    New for 2021, tinyML is developing a series of breakout sessions. Breakouts are focused on bringing focused topics directly to the audience that needs them. They will be practical and interactive discussions to foster better understanding of design and application issues, best practices, tools, and funding opportunities to accelerate the deploymen

  • January 15, 2021

    tinyML Awards 2021

    The tinyML Summit organizers are pleased to announce the creation of three awards to recognize the achievements of the industry and academia toward fulfilling the vision of ultra-low power machine learning devices at the very edge of the cloud.

  • February 12, 2021

    Breaking News On Disruptive Products And Tools

    An exciting new session at the tinyML Summit will allow a small number of time slots to companies / experts / academia to share the very latest substantial and disruptive developments and upcoming products of significance in the field of tiny machine learning. Submit your Breaking News On Disruptive Products And Tools today!

  • February 12, 2021

    tinyML Summit 2021 Sponsorship Opportunities

    Although it will be virtual, the tinyML Summit 2021 will continue the tradition of high-quality state-of-the-art presentations and we will focus more on the interactivity aspects which we know is important to sponsors. Find out more about sponsoring and supporting tinyML Foundation.

Schedule

Pacific Standard Time / UTC-8

8:00 am to 8:15 am

Open / Welcome

Evgeni GOUSEV, Senior Director, Qualcomm Research

Marian VERHELST, Associate Professor, KU Leuven

8:15 am to 9:45 am

Track 1

Tutorial: Training a Magic Wand

Pete WARDEN, Technical Lead, Google

This tutorial will show how to gather data, train, and deploy an IMU-based model for recognizing gestures on an Arduino Nano BLE Sense 33. It will use the Arduino IDE and Colab scripts to develop the model and will explain the feature generation needed to go from raw accelerometer and gyroscope data to input suitable for a neural network. Using TensorFlow Lite Micro and Arm’s CMSIS-NN library, you will learn how to create a practical application from scratch. It is recommended that you purchase the Arduino TinyML Kit to be able to follow along virtually.

Track 2

Tutorial: Image sensors for low power applications

Song CHEN, Research Scientist, Facebook Reality Labs Research

Image sensors are the front end of many computer-vision based input modalities. These human-machine input modalities usually need to run on a mobile platform which has stringent power requirement. This tutorial will cover both low power image sensor design from a designer’s perspective and some useful practices to save sensor power from a user’s perspective especially in ML applications. We will start by laying out basics including the operation principle of pixels, readout chain and other common blocks in an image sensor. Then, the trade-off between power consumption and general sensor performance will be discussed. Following the discussion, the effectiveness of power reduction techniques like subsampling, low frame rate, etc. and the impact on following ML processing stages will be evaluated with examples. Finally, an ultra-low power global-shutter digital pixel sensor developed at Facebook Reality Labs Research will be introduced.

9:45 am to 10:00 am

Break

10:00 am to 11:30 am

Track 1

Tutorial: Advanced network quantization and compression through the AI Model Efficiency Toolkit (AIMET)

Abhijit KHOBARE, Director of Software Engineering, Qualcomm Technologies, Inc. (QTI)

Chirag PATEL, Principal Engr./Mgr. in Corp. R&D AI Research team, Qualcomm Technologies, Inc. (QTI)

AI is revolutionizing industries, products, and core capabilities by delivering dramatically enhanced experiences. However, the deep neural networks of today use too much memory, compute, and energy. To make AI truly ubiquitous, it needs to run on the end device within a tight power and thermal budget. Quantization and compression help address these issues. In this tutorial, we’ll discuss:

  • The existing quantization and compression challenges
  • Our research in novel quantization and compression techniques to overcome these challenges
  • How developers and researchers can implement these techniques through the AI Model Efficiency Toolkit
Track 2

Tutorial: Build Industrial-Grade tinyML applications with Edge Impulse!

Jan JONGBOOM, CTO, Edge Impulse

Daniel SITUNAYAKE, Founding tinyML Engineer, Edge Impulse

 In this free live workshop, you will build a full tinyML application, end-to-end, using the latest best practices in embedded machine learning. You will learn how to collect a dataset, design and train a tiny (but accurate) model, evaluate its performance, optimize it for embedded use, and integrate it into a real embedded application running on a genuine MCU.

Register for this Workshop on the tinyML Summit registration form (check the Workshop box). You may either purchase the Thunderboard kit to actually build an application or simply observe. If you order the kit, in addition you may download the Open Source Firmware for the Thunderboard companion development board which is hosted on GitHub.

Pacific Standard Time / UTC-8

8:00 am to 8:15 am

Open / Welcome

Evgeni GOUSEV, Senior Director, Qualcomm Research

Marian VERHELST, Associate Professor, KU Leuven

8:15 am to 9:00 am

Keynote: Putting AI on a Diet: TinyML and Efficient Deep Learning

Song HAN, Assistant Professor, MIT EECS

Abstract (English)

Deep learning is computation-hungry and data-hungry. We aim to improve the computation efficiency and data efficiency of deep learning. First, I’ll present MCUNet[1] that brings deep learning to IoT devices. MCUNet is a framework that jointly designs the efficient neural architecture (TinyNAS) and the light-weight inference engine (TinyEngine), enabling ImageNet-scale inference on IoT devices that have only 1MB of Flash. Next I will talk about TinyTL[2] that enables on-device transfer learning, reducing the memory footprint by 7-13x. Finally, I will describe Differentiable Augmentation[3] that enables data-efficient GAN training, generating photo-realistic images using only 100 images, which used to require tens of thousand of images will be discribed. It is hopeful that such TinyML techniques can make AI greener, faster, and more sustainable.

[1] MCUNet: Tiny Deep Learning on IoT Devices, NeurIPS’20, spotlight.
[2] TinyTL: Reduce Memory, Not Parameters for Efficient On-Device Learning, NeurIPS’20
[3] Differentiable Augmentation for Data-Efficient GAN Training, NeurIPS’20

9:00 am to 9:45 am

Keynote: Many shades of acceleration – an Open TinyML Platform Perspective

Luca BENINI, Chair of digital Circuits and systems | Full Professor, ETHZ | University of Bologna

Abstract (English)

Luca Benini, Chair of digital Circuits and systems, ETHZ and Full Professor at the University of Bologna
The next wave of “Extreme Edge AI” pushes signal processing and machine learning aggressively towards sensors and actuators, with sub mW (TinyML) power budgets, while at the same time raising the bar in terms of accuracy and flexibility. To succeed in this balancing act, we need principled ways to walk the line between general-purpose and highly specialized architectures. In this talk I will detail on how to walk the line, drawing from the 40+ chips tape-out experience of the open PULP (parallel ultra-low power) platform, based on RISC-V processors coupled with domain-specific acceleration engines.

9:45 am to 10:00 am

Break

10:00 am to 10:15 am

Today’s Breakout Pitches

10:15 am to 11:00 am

tiny Talks

Performing Inference on Binarized Neural Networks with xcore.ai

Laszlo KINDRAT, Senior Technologist, XMOS

Abstract (English)

Ultra-low bitwidth neural networks have been a hot topic in tinyML community, both in terms of novel hardware accelerators, as well as software solutions for training and deployment. In particular, binarized neural networks (BNNs) show large potential due to their simple hardware requirements. xcore.ai (a fast, economical crossover processor from XMOS), has a vector unit with specialized instructions for performing inference on BNNs, which to the best of our knowledge makes it the first MCU class chip with a BNN accelerator in mass production. In this talk we describe these instructions in detail, and how they enable a theoretical maximum of 286GOps/s when executing binarized neural networks. Secondly, we give an overview of our machine learning model deployment toolchain that seamlessly integrates with Larq, a popular open-source framework for training binarized neural networks. Finally, we present performance benchmarks on image classification models with various combinations of binarized and 8bit quantized layers.

Compute-in-Memory Hardware Accelerator for Always-On TinyML

Sameer WADHWA, Senior Director, Qualcomm

Supporting Tensorflow Lite MCU in tiny low power FPGAs

Hoon CHOI, Fellow, Lattice Semiconductor

Abstract (English)

The arena of cost optimized, high performance Edge accelerators is growing increasingly competitive with a variety of architectures to choose from when implementing an AI capable system. As new generation of Edge applications emerges, designers are increasingly pressed to develop solutions that combine low power and low latency, they require easy to use and flexible accelerators.

Lattice’s FPGAs are uniquely positioned to address the rapidly changing world for Edge devices. This class of FPGAs possess the parallel processing capabilities inherent in FPGAs to accelerate neural network performance and are HW programmable to keep up with the fast pace of changing ML algorithms. They are designed with higher on chip memory, optimized DSP blocks and compute resources distributed through the fabric for workload acceleration resulting in a low power system implementation.

To provide a software programmable solution that is easy to use, support for TF Lite with soft RISC-V was implemented on the FPGA fabric. Creating best of both world, programmable device with flexible acceleration blocks running on HW to enable developers with or without FPGA expertise to build their systems more quickly. Comparing TF Light implementation on ARM M4 based CPU vs. FPGA of comparable size/cost, the FPGA runs 2~10x faster than the MCU for a comparable power consumption.
In this presentation, we cover the details of the accelerators we designed, the limitations we faced that hindered further optimizations in accelerators, and possible solutions to the limitations.

11:00 am to 12:00 pm

Panel Discussion

Opportunities at the Edge: Venture and tinyML

Moderator: Kurt KEUTZER, Full Professor, University of California

Chris ROWEN, VP of Engineering, Cisco

Pushing machine learning into ultra-low-power applications at the edge isn’t just an academically compelling idea, it is a potentially disruptive shift in mass-market technology. In this panel we’ve gathered four distinguished venture capitalists to look at tinyML opportunities through an entrepreneurial lens. In particular we have asked them to consider:

  • What makes you interested in investment opportunities for machine learning at the edge?
  • What is your general advice to tech entrepreneurs: build a horizontal platform for broad application or target a particular vertical?
  • What are some of the particular near-term opportunities for venture investment at the edge that you find especially exciting?
  • How might VC’s value a tinyML-startup – how much is it driven by the target market, the team, the technology, or the data?
  • And the $6.4B question: what is the future killer app at the edge?

12:00 pm to 1:00 pm

Session 1

Hardware Optimization

Ultra-low Power and Scalable Compute-In-Memory AI Accelerator for Next Generation Edge Inference

Behdad YOUSSEFI, Founder and CEO, Areanna AI

Abstract (English)

Edge AI hardware accelerators are either deployed on Edge servers where sophisticated AI models run on a power budget between 1-10 Watts or on Edge devices where simple AI models run at milliwatts of power. But implementing more sophisticated AI models on Edge devices requires further development of ultra-low power architectures.

Research has shown that power consumption is dominated by data communication between memory and processor. To minimize data movement, the Compute-In-Memory (CIM) architecture has been explored by companies/academics. CIM is inherently a mixed signal architecture and hence requires data converters to interface between layers of network. However, data converters have proven to be the Achilles’ heel of this architecture as they take up to 98% of overall chip area and consume more than 85% of overall power consumption, defeating the whole purpose of CIM architecture. CIM also suffers from analog nonidealities which can degrade AI performance. Furthermore, the extra processing steps needed to fabricate the memory array in CIM limits the scalability of this architecture.

Areanna’s architecture addresses these issues using our proprietary Compute-and-Quantize-In-Memory (CQIM) architecture where SRAM bit-cells are repurposed to construct data converters, improving power/area efficiency by over an order of magnitude. Using logic gates as its building blocks, CQIM is inherently a digital architecture and scales well with the latest process nodes. High power efficiency and scalability of this architecture brings deployment of sophisticated real-time AI models with mW power budget within reach. A CQIM prototype is implemented and taped out in standard CMOS process.

CUTIE: Multi-PetaOP/s/W Ternary DNN inference Engine for TinyML

Moritz SCHERER, PhD Student, ETH Zürich

Session 2

Partner Sessions

Partner Sessions

Session 3

tinyML applications

Session 4

tinyML vision challenge

Session 5

Birds of a feather #1

Session 6

tinyML for Good — Conservation

Pacific Standard Time / UTC-8

8:00 am to 8:15 am

Opening and Award Announcements

8:15 am to 9:00 am

Keynote: miliJoules for 1000 Inferences: Machine Learning Systems “on the Cheap”

Diana MARCULESCU, Department Chair, Cockrell Family Chair for Engineering Leadership #5, The University of Texas at Austin

Keynote

Abstract (English)

Machine learning (ML) applications have entered and impacted our lives unlike any other technology advance from the recent past. While the holy grail for judging the quality of a ML model has largely been accuracy and only recently its resource usage, neither of these metrics translate directly to energy efficiency, runtime, or mobile device battery lifetime. This talk uncovers the need for designing efficient convolutional neural networks (CNNs) for deep learning mobile applications that operate under stringent energy and latency constraints. We show that, while CNN model quantization and pruning are effective tools in bringing down the model size and resulting energy cost by up to 1000x while maintaining baseline accuracy, the interplay between bitwidth, channel count, and CNN memory footprint uncovers a non-trivial trade-off. Surprisingly, our results show that when the channel count is allowed to change, a single weight bitwidth can be sufficient for model compression, which greatly reduces the software and hardware optimization costs for CNN-based ML systems.

9:00 am to 9:45 am

Keynote: Adaptive Neural Networks for Agile TinyML

Sek CHAI, Co-founder and CTO, Latent AI

Abstract (English)

We present a new way to run your neural network that dynamically minimizes the working footprint for both memory and compute horsepower. Such a formulation requires retraining the network in a way that offers runtime flexibility during inference. Ultimately, the dynamic neural network is highly agile and can self-regulate to minimize computational needs.

9:45 am to 10:00 am

Break

10:00 am to 10:15 am

Today’s Breakout Pitches

10:15 am to 11:00 am

tiny Talks

Building Computer Vision Applications Under Extreme Constraints: Lessons from the Field

Koen HELWEGEN, Deep Learning Scientist, Plumerai

Abstract (English)

We present various computer vision applications on microcontrollers that are enabled by Binarized Neural Networks (BNNs). This includes state-of-the-art models on the Arm Cortex-M4 architecture for the Visual Wake Words benchmark task (84.5% accuracy with under 170ms latency on a STM32F407VG) and person detection with bounding boxes. Moving beyond artificial benchmarks, we demonstrate the performance in real-world settings by deploying on an off-the-shelf Arm Cortex-M4 microcontroller with an inexpensive, low-power OV2680 camera. These applications are built using our integrated stack for training and inference of BNNs as well as through the collection, labeling and monitoring of custom designed datasets for TinyML. This combination results in highly-accurate and highly-efficient BNN models for cheap, low-power microcontrollers. We discuss practical tips for developing demanding computer vision applications on microcontrollers and highlight some of the lessons we learnt while developing BNNs for the real-world, such as our emphasis on high-quality, richly annotated data and powerful, hardware-based neural architecture search.

Hardware aware Dynamic Inference Technology

Vikrant TOMAR, Founder and CTO, Fluent.ai

Abstract (English)

There has been a recent surge in research in dynamic inference technologies to reduce the cost of inference without sacrificing the accuracy of the model. These models are based on the assumption that not all parts of the output feature map (OFM) are equally important for all inputs. The parts of the output feature maps that are deemed unimportant for a certain input can be skipped entirely or computed at a lower precision leading to reduced number of computation. This can enable faster inference of a large network leading to high accuracy. However, we show that the two popular methods that optimize different aspects of the OFM (channel and spatial) lead to sparse matrix multiplication during inference on a CPU which can lead to poor run-time characteristics in-spite of reduced number of MAC operations. We show a way to make these techniques SIMD Vector Length aware leading to block sparse matrices which can run more efficiently on a hardware with vector compute units. Our technique allows these models to create blocks of vector length 2, 4 and 8 with minimal loss in accuracy beating traditional pruning methods by a large margin for image classification task.

11:00 am to 12:00 pm

Panel Discussion

tinyML inference SW – where do we go from here?

Moderator: Ian BRATT, Distinguished Engineer & Fellow, Arm

Moderator: Ofer DEKEL, Partner Research Area Manager, Microsoft Research

Join a collection of industry experts as we discuss the current state and potential future of tinyML inference SW. What is missing today, what new technologies will impact tinyML inference SW, and how do we go forward as a community?

12:00 pm to 1:00 pm

Session 1

Algorithms and Tools

Neutrino: A BlackBox Framework for Constrained Deep Learning Model Optimization

Davis SAWYER, Co-Founder & Chief Product Officer, Deeplite

Hardware Aware Training for Efficient Keyword Spotting on General Purpose and Specialized Hardware

Chris ELIASMITH, Co-CEO, Applied Brain Research

Abstract (English)

Keyword spotting (KWS) provides a critical user interface for many mobile and edge applications, including phones, wearables, and cars. As KWS systems are typically ‘always on’, maximizing both accuracy and power efficiency are central to their utility. In this work we use hardware aware training (HAT) to build new KWS neural networks based on the Legendre Memory Unit (LMU) that achieve
state-of-the-art (SotA) accuracy and low parameter counts. This allows the neural network to run efficiently on standard hardware (212 µW). We also characterize the power requirements of custom designed accelerator hardware that achieves SotA power efficiency of 8.79 µW, beating general purpose low power hardware (a microcontroller) by 24x and special purpose ASICs by 16x.

Low-precision Winograd Convolution over Residue Number System

Zhi-Gang LIU, Research Engineer, Arm

Abstract (English)

The low-precision (8 or sub-8bit) convolutional neural networks consume a fraction of memory footprint and power comparing to high-precision models running on mobile or embedded devices. The classical fast Winograd convolution algorithm requires high-precision floating-point operation and thus fails to accelerate the low-precision CNN. So, the current state-of-the-art low-precision convolution is a GEMM based approach relying on im2col or im2row transformations to convert the convolution into GEMM operation and each output demands 9 MAC operations for popular 3×3 filter, 25 ops for 5×5 filter. This work extends the Winograd algorithm to modular arithmetic and explores the optimized implementation of the fast low-precision convolution for ultra-low power machine learning (ML) at the edge. The new approach has arithmetic reduction up to 6.8x corresponding to 16×16 transformation tiles and only relies on int8 or int16 op which are well supported by commodity edge devices. We evaluated the performance of proposal with sub-8bit VGG16 and ResNet50v1 models on ImageNet dataset using Arm cortex A53 cpu and M7 mcu and observed more than 2x convolution latency reduction.

An Introduction to an Open-Source Fixed-Point Inference Framework – NNoM

Jianjia MA, Research Fellow, University of Southampton

Session 2

Partner Sessions

Session 3

Birds of a Feather #2

Session 4

The tinyML Market

Session 5

tinyML for Good — STEM Education

Pacific Standard Time / UTC-8

8:00 am to 8:15 am

Opening and Awards Ceremony

8:15 am to 9:00 am

Keynote: Efficient Audio-Visual Understanding on AR Devices

Vikas CHANDRA, Director, AI, Facebook Reality Labs

Abstract (English)

Augmented reality (AR) is a set of technologies that will fundamentally change the way we interact with our environment. It represents a merging of the physical and the digital worlds into a rich, context aware user interface delivered through a socially acceptable form factor such as eyeglasses. The majority of these novel experiences in AR systems will be powered by AI because of their superior ability to handle in-the-wild scenarios. A key AR use case is a personalized, proactive and context-aware Assistant that can understand the user’s activity and their environment using audio-visual understanding models. In this presentation, we will discuss the challenges and opportunities in both training and deployment of efficient audio-visual understanding on AR glasses. We will discuss enabling always-on experiences within a constrained power budget using cascaded multimodal models, and co-designing them with the target hardware platforms. We will present our early work to demonstrate the benefits and potential of such a co-design approach and discuss open research areas that are promising for the research community to explore.

9:00 am to 9:45 am

Keynote: Data-Free Model Compression

Mohammad RASTEGARI, Senior AI/ML Technical Leader, Apple

Keynote

Abstract (English)

Efficient method for compressing a trained neural network without using any data is very challenging. Our data-free method requires 14x-450x fewer FLOPs than comparable state-of-the-art methods. We break the problem of data-free network compression into a number of independent layer-wise compressions. We show how to efficiently generate layer-wise training data, and how to precondition the network to maintain accuracy during layer-wise compression. We show state-of-the-art performance on MobileNetV1 for data-free low-bit-width quantization. We also show state-of-the-art performance on data-free pruning of EfficientNet B0 when combining our method with end-to-end generative methods.

9:45 am to 10:00 am

Today’s Breakout Pitches

10:15 am to 10:45 am

Insights from a Multi-Purpose Self-Learning Smart Sensor

Kaustubh GANDHI, Senior Product Manager Software, Bosch Sensortec

Abstract (English)

Edge-AI devices need to ensure context-sensitive adaptation and real-time personalization for end-users. In this talk, we introduce some insights gained while designing Bosch’s novel self-learning sensor.

The sensor’s self-learning function enables the device to learn new motion patterns in-use directly from the end-user, to personalize built-in patterns directly for an end-user and automatically classify and count the movement types in real-time, all within the sensor itself.

In spite of delivering an AI experience, the function runs on sensor’s co-processor with ca. 300 µA and memory under 50 KB, while yet delivering over 90% accuracy for personalized home workouts. This is significant improvement for learning at the edge on wrist and in-ear wearables.

Secondly, as the sensor is capable of switching to a different function in run-time, sensor purpose can change depending on user’s context, such as the orientation and position tracking during running, style classification during swimming or personalization during fitness workouts.

Thirdly, the design allows the self-learning feature to utilize an expandable list of virtual sensors from sensor data fusion (e.g. quaternions) and peripherals (e.g. magnetometer, pressure sensors).
This enables faster and robust pattern detection from an expandable list of input sources, chosen according to target application, as against to pre-programmed AI solutions with fixed inputs.

In summary, in order to realize true potential of edge-AI, it is important to design the software with capabilities to learn and adapt to the end-user while maintaining scalability for diverse applications.

10:45 am to 11:45 am

Breaking News on Disruptive Products and Tools

11:45 am to 12:00 pm

Break

12:00 pm to 1:00 pm

Session 1

Environmental Noise Classification on Microcontrollers

Jon NORDBY, CTO, Soundsensing

Abstract (English)

Noise is a growing problem in urban areas, and according to the WHO is the second environmental cause of health problems in Europe.
Noise monitoring using Wireless Sensor Networks are being applied in order to understand and help mitigate these noise problems. It is desirable that these sensor systems, in addition to logging the sound level, can indicate what the likely sound source is. Performing such Environmental Noise Classification directly in the sensor is desirable in order to avoid sending audio data to the cloud, which may have negative impacts on data transfer amounts, battery lifetime and privacy.

In this talk we will explain how we tested several different Convolutional Neural Networks for this task on the STM32L476 low-power microcontroller, and the results we were able to achieve on the Urbansound8k dataset. Several techniques such Depthwise-Separable convolutions, striding for downsampling, reducing input dimensionality was tested in order to make the CNN models as efficient as possible, and these will likely be useful also for other audio or image tasks.

The research was initially carried out as part of a master thesis at the Norwegian University of Life Sciences (NMBU). Since then, we have continued to work on this topic at Soundsensing, and we will share some of the progress and challenges in bringing this kind of research to market.

Real-World Performance Analysis of Visual Wake Words

Luke BERNDT, Senior Director, In-Q-Tel

Abstract (English)

The Google Visual Wake Words paper (Chowdhery et al., 2019) proposes techniques for creating object recognition models appropriate for microcontrollers. The paper demonstrates an accurate person detection model trained using the Microsoft Common Objects in Context (COCO) dataset. Because the COCO dataset is built on photographs found internet photography sites and because these images are composed by a photographer, the COCO dataset, we hypothesize, may be ill-suited for tinyML visual sensors. Typical visual sensors often have unusual perspectives of an object, which can result in poor object recognition.
We therefore investigated model performance on classes other than persons, evaluated performance by deploying the model on hardware in the wild, and then built a novel dataset for real world testing. In certain real-world environments, we found a decrease in accuracy of over 50%. Additionally, we investigated transfer learning and techniques for identifying blind spots in models to better target the augmentation of objects in the dataset. We find that extra care is needed when using general-purpose image datasets, like COCO, to train models for tinyML based visual sensors.

Session 2

Partner Sessions

Session 3

Grants (Government Agencies & Industry)

Session 4

Birds of a feather #3

Session 5

tinyML for Good — Health (Water, Cancer, Covid, Pandemics)

8:00 am to 1:20 pm

tinyML Research Symposium

Schedule for the inaugural tinyML Research Symposium.

Schedule subject to change without notice.

Committee

Marian VERHELST

Technical Program Chair

KU Leuven

Peter VAJADA

Technical Program Vice-Chair

Facebook

Edith BEIGNÉ

Facebook

Ian BRATT

Arm

Ofer DEKEL

Microsoft Research

Ira FELDMAN

tinyML Foundation

Adam FUKS

NXP

Evgeni GOUSEV

General Chair

Qualcomm Research

Kurt KEUTZER

University of California

Boris MURMANN

Stanford University

Chris ROWEN

Cisco

Moritz SCHERER

ETH Zürich

Zach SHELBY

Edge Impulse

Steve WHALLEY

Strategic World Ventures

Wei XIONG

Hoi-Jun YOO

KAIST

Speakers

Raziel ALVAREZ

Facebook

Luca BENINI

ETHZ | University of Bologna

Luke BERNDT

In-Q-Tel

Luis CEZE

OctoML

Sek CHAI

Latent AI

Vikas CHANDRA

Facebook Reality Labs

Song CHEN

Facebook Reality Labs Research

Hoon CHOI

Lattice Semiconductor

Bill COUGHRAN

Sequoia Capital

Chris ELIASMITH

Applied Brain Research

Kaustubh GANDHI

Bosch Sensortec

Song HAN

MIT EECS

Koen HELWEGEN

Plumerai

Jan JONGBOOM

Edge Impulse

Kurt KEUTZER

University of California

Laszlo KINDRAT

XMOS

Abhijit KHOBARE

Qualcomm Technologies, Inc. (QTI)

Samir KUMAR

M12

Chris LATTNER

SiFive

Zhi-Gang LIU

Arm

Jianjia MA

University of Southampton

Diana MARCULESCU

The University of Texas at Austin

Jon NORDBY

Soundsensing

Chirag PATEL

Qualcomm Technologies, Inc. (QTI)

Mohammad RASTEGARI

Apple

Chris ROWEN

Cisco

Davis SAWYER

Deeplite

Moritz SCHERER

ETH Zürich

Daniel SITUNAYAKE

Edge Impulse

Eileen TANGHAL

In-Q-Tel

Urmish THAKKER

Stealth

Tianqi CHEN

OctoML

Vikrant TOMAR

Fluent.ai

placeholder

Sameer WADHWA

Qualcomm

Pete WARDEN

Google

Behdad YOUSSEFI

Areanna AI

Sponsors

( Click on a logo to get more information)