tinyML EMEA Technical Forum 2021

Enabling ultra-low Power Machine Learning at the Edge

June 7-10, 2021

Event will be held in Central European Time (CET)

June 7-10, 2021

Inaugural tinyML EMEA Technical Forum

tinyML events are going “global”, virtually. After postponing the in-person event that was to be held in Cyprus, we will be going online the week of June 7, 2021. Even though it is virtual it will still be a “regional” event, with speakers and participants showcasing technology from the Europe, Middle East, and Africa (EMEA) region.

tinyML is a fast growing branch of machine learning technologies, architectures and approaches dealing with machine intelligence at the very edge. It is broadly defined as integrated, “full-stack” (HW-SYS-SW-apps), ML architectures, techniques, tools and approaches capable of performing on-device analytics for a variety of sensing modalities (vision, audio, motion, environmental, human health monitoring etc.) at extreme energy efficiency, typically in the single mW (and below) power range, enabling machine intelligence right at the boundary of the physical and digital worlds.

Venue

Virtual - online

Contact us

Bette COOPER

News

April 04, 2021

tinyML EMEA 2021 Call for Presentations & Posters

Call for Presentation and Poster for tinyML EMEA Technical Forum to be held virtually June 7-10, 2021. Please submit your abstracts right away.

April 06, 2021

tinyML EMEA 2021 Sponsorship Opportunities

Find out more about sponsoring the tinyML EMEA Technical Forum 2021 and supporting the tinyML Foundation.

Schedule

Central European Time / UTC +1

4:00 pm to 4:15 pm

Open / Welcome

4:15 pm to 5:15 pm

Tutorial: Bio-inspired neuromorphic circuits architectures

Giacomo INDIVERI, Professor, ETH Zurich

Abstract (English)

Artificial Intelligence (AI) and deep learning algorithms are revolutionizing our computing landscape, and have demonstrated impressive results in a wide range of applications. However, they still have serious shortcomings for use cases that require closed-loop interactions with the real-world.

Current AI systems are still not able to compete with biological ones in tasks that involve real-time processing of sensory data and decision making in complex and noisy settings.
Neuromorphic Intelligence (NI) aims to fill this gap by developing ultra-low power electronic circuits and radically different brain-inspired in-memory computing architectures.

NI hardware systems implement the principles of computation observed in the nervous system by exploiting the physics of their electronic devices to directly emulate the biophysics of real neurons and synapses.

This tutorial will present strategies derived from neuroscience for carrying out robust and low latency computation using electronic neural computing elements that share the same (analog, slow, and
noisy) properties of their biological counterparts. I will present examples of NI circuits, and demonstrate applications of NI processing systems to extreme-edge use cases, that require low power, local processing of the sensed data, and that cannot afford to connect to the cloud for running AI algorithms.

5:15 pm to 6:15 pm

Tutorial: Context Awareness Function Pack (FP)

Lisa TROLLO, Artificial Intelligence Strategy, STMicroelectronics

Federico IACCARINO, Product Marketing, STMicroelectronics

Carlo PARATA, System Engineer, STMicroelectronics

Abstract (English)

This live tutorial will feature experts from ST Microelectronics covering the joint use of STM32 and In-sensor computing with machine learning core. The agenda is aligned to the subject as follows:

introduction of ST products for edge AI for both STM32 and sensors
describe ML/AI ecosystem in term of tools to be used for FP
description and usage of the FP for ASC and HAR on the boards

The tutorial is not hands-on; rather it is a How to Get Started plus and will include information for attendees will be able to buy the boards, install and run the FP after the tutorial.

Central European Time / UTC +1

4:00 pm to 4:15 pm

Open / Welcome

4:15 pm to 5:00 pm

Keynote: A novel approach to building exceptionally tiny, predictive and explainable models for non-data scientists

Blair NEWMAN, CTO, Neuton

Abstract (English)

Performing compute and inference on the edge solves most issues with privacy, latency and reliability, but how do we address the remaining obstacles:
many parties interested in AI/ML, including those who work with microcontrollers, do not have knowledge in Machine Learning and software development
the difficulty of embedding large ML models into small compute devices
the challenge of evaluating the quality of a model, and whether it has interpretable, explainable and reliable output
Inference on edge devices will move toward mass adoption only if Machine Learning becomes available to non-Data Scientists. We will show how already, today, non-ML users can build – with just a few clicks and no-code – compact models which are up to 1000 times smaller than those built with Tensor Flow and similar frameworks (and without reduction of accuracy). We will demonstrate why models built with those frameworks are not optimal in size and accuracy and share how to overcome those obstacles and build quality compact models with an excellent generalization capability.
We will explain and show examples of how Neuton’s working tiny models can be embedded into microcontrollers and will compare the results with those built with TensorFlow Lite. We will also demonstrate how users can evaluate model quality at every stage and identify the logic behind the model analysis, therefore clarifying why certain predictions have been made.

5:00 pm to 5:45 pm

Keynote: The model efficiency pipeline, enabling deep learning inference at the edge

Bert MOONS, Research Scientist, Qualcomm

Abstract (English)

Today, most deep learning and AI applications are developed on and for high-performance computing systems in the cloud. In order to make them suitable for real-time deployment on low-power edge devices and wearable platforms, they have to be specifically optimized. This talk is an overview of a model-efficiency pipeline that achieves this goal: automatically optimizing deep learning applications through Hardware-Aware Neural Architecture Search, compressing and pruning redundant layers and subsequently converting them to low-bitwidth integer representations with state-of-the-art data-free and training-based quantization tools. Finally, we take a sneak peek at what’s next in efficient deep learning at the edge: mixed-precision hardware-aware neural architecture search and conditional processing.

5:45 pm to 6:30 pm

tiny Talks

Because we will be virtual, and since we know that nobody wants to sit through a traditional 30-minute talk online we will have a series of “tiny Talks” which will be 15 minutes total, with a quick 12-minute speaking time and additional time for the moderator to lead a Q&A session. The talks might feature a specific application, tools, demo, technology innovation or other relevant topics to tinyML.

Presenters to be announced.

6:30 pm to 7:30 pm

Partner Sessions

These sessions will be an opportunity to hear from commercial companies in the tinyML ecosystem on market and technology trends they are addressing to enable the exponential growth of tinyML solutions.

Others to be announced

Avoiding Loss of Quality while in Pursuit of a Tiny Model

Blair NEWMAN, CTO, Neuton

Abstract (English)

We can see that today the entire tinyML community is focused on solving the model shrinking issue. We are confident that the issue of assessing the quality of the model and its explainability is already relevant for the entire tinyML community, and we will share how we approach this challenge.

In this talk, we’ll show how incredibly compact models can be created without losing focus on precision. During the talk, we plan to provide answers to the following questions, particularly relevant to the tinyML community at this time:

How, in the pursuit of a small model, can we avoid loss of quality?

Is there a choice between model accuracy and size, today?

How can the quality of a model be evaluated, at all stages, without need for a data scientist?

How can the logic of decision making by a model be identified and understood, if you are dealing with a neural network?

How can available training data be evaluated, and the most important statistics in the context of a single variable, overall data, interconnections, and in relation to the target variable in a training dataset be clearly understood?

How can the reason why this particular model made this or that decision be identified? How can a model’s output be interpreted? Do models built with Neural Networks have explainability potential?

Do all parameters from a data source sensor need to be collected to build a model and obtain meaningful insights? What parameters are enough to build a tiny model?

How can the influence and relative importance of every parameter be understood, on the output?

Can the input parameters be emulated to see how output changes and why?

How can the quality of a tiny model be evaluated?

How can model decay, and need for retraining, be automatically identified?

How can the quality of every single prediction be thoroughly evaluated? How can credibility of each prediction be understood and measured, and how can the level of confidence in each prediction be evaluated?

Central European Time / UTC +1

4:00 pm to 4:15 pm

Open / Welcome

4:15 pm to 5:00 pm

Keynote: Bottom-up and top-down neural processing systems design: unveiling the road toward neuromorphic intelligence

Charlotte FRENKEL, Postdoctoral Researcher, Institute of Neuroinformatics

Abstract (English)

While Moore’s law has driven exponential computing power expectations, its nearing end calls for new roads to embedded cognition. The field of neuromorphic computing aims at a paradigm shift compared to conventional von-Neumann computers, both for the architecture (i.e. in-memory computing) and for the data representation (i.e. spike-based event-driven encoding). In this talk we will show how to best exploit a bottom-up (neuroscience-driven) approach and a top-down (application-driven) one toward embedded cognition and neuromorphic intelligence. The talk is thus divided in two parts.

In the first part we will focus on the bottom-up approach. From the building-block level to the silicon integration, we design two digital time-multiplexed spiking neural network processing devices: ODIN and MorphIC. Furthermore, we explore the design of neuromorphic processors that use mixed-signal analog-digital circuits and temporal dynamics matched to the one of their input signals, without having to resort to time-multiplexing. We demonstrate with silicon measurement results that hardware-aware neuroscience model design and selection allows optimizing a tradeoff between biophysical versatility, neuron and synapse densities, and power consumption.

In the second part of this talk we will follow a top-down approach. By starting from the applicative problem of adaptive edge computing, we derive a learning algorithm optimized for low-cost on-chip learning: the Direct Random Target Projection (DRTP) algorithm. With silicon measurement results of a top-down DRTP-enabled neuromorphic processor codenamed SPOON, we demonstrate that combining event-driven and frame-based processing with weight-transport-free update-unlocked training supports low-cost adaptive edge computing with spike-based sensors.

Therefore, each of these two design approaches can act as a guide to address the shortcomings of the other. We compare them and discuss their tradeoffs for different potential use cases in edge computing.

5:00 pm to 5:45 pm

Keynote: tinyML Beyond Audio and Vision

Wolfgang FURTNER, Distinguished Engineer System Architecture, Infineon Technologies

Abstract (English)

This talk introduces you to a few sensors beyond microphones and cameras and to what embedded ML applications are interesting for these sensors. In particular radar sensors and environmental sensors are addressed. It illustrates the specific challenges of this sensors and how advances in AIML can be also leveraged for their application. The presentation discusses the processing needs for this sensors and gives implementation examples on small microcontrollers. It will provide guidelines for the choice of processing architectures and compare their performances. Finally it concludes with an outlook on future embedded hardware and software.

5:45 pm to 6:30 pm

tiny Talks

Because we will be virtual, and since we know that nobody wants to sit through a traditional 30-minute talk online we will have a series of “tiny Talks” which will be 15 minutes total, with a quick 12-minute speaking time and additional time for the moderator to lead a Q&A session. The talks might feature a specific application, tools, demo, technology innovation or other relevant topics to tinyML.

Presenters to be announced.

6:30 pm to 7:30 pm

Partner Sessions

These 15 minute sessions will be an opportunity to hear from commercial companies in the tinyML ecosystem on market and technology trends they are addressing to enable the exponential growth of tinyML solutions.

Others to be announced.

tinyML for Good

During this panel discussion entitled tinyML for Good, several Arm experts will be outlining how they are using tinyML applications that are focused on the environment and sustainability. They will talk about what has worked and more importantly, what has not worked for them. Prepare to listen and participate in a lively chat about tinyML for Good.

Central European Time / UTC +1

4:00 pm to 4:15 pm

Open / Welcome

4:15 pm to 5:00 pm

Keynote - TBA

5:00 pm to 5:45 pm

Panel Discussion

Growing the tinyML Community in the EMEA Region

Moderator: Tijmen BLANKEVOORT , Senior Staff Engineer Deep Learning, Qualcomm

Gian Marco IODICE, Team and Tech Lead in the Machine Learning Group, Arm

Loic LIETAR, CEO, Greenwaves

Abbas RAHIMI, Research Staff Member, ETH Zurich

Patricia SCANLON , Founder and Executive Chair, SoapBox Labs

Abstract (English)

In the EMEA region, we have a strong presence in both research and industry for digital, analog and mixed signal hardware and sensors and software for IoT, automotive among many other areas. While there are many good initiatives for collaboration, sometimes publicly funded, often also at local levels, it is often a challenge to align across geography and across academia and industry. In this panel we have gathered four experts in tinyML from academia and industry to discuss the unique strengths in EMEA to enable machine learning at the edge. In addition, we will ask them: what are we missing? What are the key challenges to tackle? How can we improve collaboration on the topic in the region?

5:45 pm to 6:00 pm

Introduction to Student Forum: The Butterfly Effect of tinyML

Vijay JANAPA REDDI, Associate Professor, Harvard University

A small change can make much bigger changes happen; one small incident can have a big impact on the future.

6:00 pm to 6:30 pm

Room 1

Student Forum

As part of the TinyML EMEA technical forum we invited students to submit poster abstracts that highlight their work in the area of machine learning at the edge or embedded edge machine learning.

The posters will be accompanied by a 3-5 minute live talk from the students to present current results and future research. The video poster and live Q&As will be recorded and posted in the tinyML YouTube channel after the Forum.

6:00 pm to 8:00 pm

Room 2

tinyML EMEA community building: matchmaking and networking session

The Horizon Europe Program and other national and EMEA regional programs are what drives research and innovation opportunities beyond the industrial initiatives. Specifically, the EMEA institutions have been actively involved in research and innovation activities funded by national and international programs. To participate in such programs, collaboration between various stakeholders is imperative! Realizing this, the tinyML EMEA Forum Organizing Committee is organizing this break-out session where such research and innovation programs and opportunities relevant to the EMEA tinyML community will be presented and discussed amongst attendees, providing an ideal networking opportunity for EMEA-based academia, industry, and all other interested entities and stakeholders, to identify, discuss and explore the possibility of joint undertaking activities in forming consortia and collaborating towards taking advantage of the funding opportunities. During the session, there will be short talks from policy makers (names to be confirmed), success stories from ongoing projects and national initiatives and networking activities such as meetup groups. Topics will include:
• Policy Makers
• Success Stories – Projects relevant to tinyML
• National Initiatives and Activities

Schedule subject to change without notice.

Committee

Theocharis THEOCHARIDES

Technical Program Chair

University of Cyprus

Peter DEBACKER

Technical Program Vice-Chair

imec

Luca BENINI

ETHZ | University of Bologna

Dominic BINKS

Audio Analytic

Tijmen BLANKEVOORT

Qualcomm

Tomas EDSÖ

Arm

Evgeni GOUSEV

General Chair

Qualcomm Research

Alessandro GRANDE

Edge Impulse

Tal HENDEL

Emza Visual Sense

Christos KYRKOU

KIOS Research and Innovation Center of Excellence

Daniel MÜLLER-GRITSCHNEDER

Chair of Electronic Design Automation

Blair NEWMAN

Neuton

Danilo PAU

STMicroelectronics Italia

Marios M. POLYCARPOU

University of Cyprus

Carlo Reita

CEA-Leti

Andreas SPANIAS

Arizona State University

Marian VERHELST

KU Leuven

Speakers

Tijmen BLANKEVOORT

Qualcomm

Charlotte FRENKEL

Institute of Neuroinformatics

Wolfgang FURTNER

Infineon Technologies

Federico IACCARINO

STMicroelectronics

Giacomo INDIVERI

ETH Zurich

Gian Marco IODICE

Arm

Vijay JANAPA REDDI

Harvard University

Loic LIETAR

Greenwaves

Colette MALONEY

DG CONNECT, European Commission

Bert MOONS

Qualcomm

Blair NEWMAN

Neuton

Carlo PARATA

STMicroelectronics

Abbas RAHIMI

ETH Zurich

Patricia SCANLON

SoapBox Labs

Lisa TROLLO

STMicroelectronics

Sponsors

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