The advancement of Artificial Intelligence (AI) and its swift deployment on resource-constrained tiny systems relies on both design quality and design efficiency of models. In this talk, we first introduce efficient AI models via hardware-friendly model compression and topology-aware Neural Architecture Search to optimize quality-efficiency trade-off on AI models. Then, we involve cross-optimization design and efficient distributed learning to brew swift and scalable AI systems with specialized hardware. Finally, we demonstrate the enhancement on quality-efficiency trade-off on alternative applications and scenarios, such as Electronic Design Automation (EDA) and Adversarial Machine Learning. Through these explorations, we present our vision on the future of the full stack of tiny AI solutions.
Software/Hardware Co-design for Tiny AI Systems
Yiran CHEN, Professor
Yiran CHEN, Professor
Yiran Chen received B.S (1998) and M.S. (2001) from Tsinghua University and Ph.D. (2005) from Purdue University. After five years in industry, he joined University of Pittsburgh in 2010 as Assistant Professor and then was promoted to Associate Professor with tenure in 2014, holding Bicentennial Alumni Faculty Fellow. He is now the Professor of the Department of Electrical and Computer Engineering at Duke University and serving as the director of the NSF AI Institute for Edge Computing Leveraging the Next-generation Networks (Athena), the NSF Industry–University Cooperative Research Center (IUCRC) for Alternative Sustainable and Intelligent Computing (ASIC), and the co-director of Duke Center for Computational Evolutionary Intelligence (DCEI). His group focuses on the research of new memory and storage systems, machine learning and neuromorphic computing, and mobile computing systems. Dr. Chen has published 1 book and about 500 technical publications and has been granted 96 US patents. He has served as the associate editor of more than a dozen international academic periodicals and served on the technical and organization committees of more than 60 international conferences. He is now serving as the Editor-in-Chief of the IEEE Circuits and Systems Magazine. He received eight best paper awards, one best poster award, and fourteen best paper nominations from reputable international conferences and workshops such as MICRO, KDD, DATE, SEC, etc. He received numerous awards for his technical contributions and professional services such as IEEE Computer Society Edward J. McCluskey Technical Achievement Award, ACM SIGDA Service Award, etc. He is a Fellow of the ACM and IEEE and now serves as the chair of ACM SIGDA.
Schedule subject to change without notice.