Theocharis (Theo) Theocharides is an Associate Professor in the Department of Electrical and Computer Engineering and the Research Director at the KIOS Research and Innovation Center of Excellence at the University of Cyprus. Theocharis received his Ph.D. in Computer Engineering from Penn State University, working in the areas of low-power computer architectures and reliable system design with emphasis on computer vision and computational intelligence applications. Theocharis was honored with the Robert M. Owens Memorial Scholarship in May 2005. He has been with the Electrical and Computer Engineering department at the University of Cyprus since 2006, where he directs the Embedded and Application-Specific Systems-on-Chip Laboratory and with the KIOS CoE since its inception in 2008. His research focuses on the design, development, implementation and deployment of low-power and reliable on-chip application-specific architectures, low-power VLSI design, real-time embedded systems design and exploration of energy-reliability trade-offs for Systems on Chip and Embedded Systems. His focus lies on acceleration of computer vision and artificial intelligence algorithms in hardware, geared towards edge computing, and in designing self-aware, evolvable edge computing systems. He serves on several organizing and technical program committees of various conferences and is currently serving as the Application Track Chair for DATE. Theocharis is a Senior Member of the IEEE, a member of the ACM, and an Associate Editor for IEEE Consumer Electronics magazine, ACM Transactions on Embedded Computing Systems, and the ETRI journal. He also serves on the Editorial Boards of IEEE Design & Test magazine.

Peter Debacker received the M.Sc. (Hons.) degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 2004. He worked with Philips as a system engineer and at Essensium as a System Architect before joining IMEC, Leuven, in 2011. He is currently Program Manager in the Semiconductor Technology and Systems division. He leads a team that researches semiconductor technology, architecture and algorithms to create efficient AI hardware ranging from DNN accelerators, to in-memory compute and neuromorphic hardware. Besides AI specific hardware, he works on power-performance-area (PPA) optimization of scaled CMOS technologies (for 3nm and beyond), emerging memories and beyond CMOS technologies. In his past he has worked on IMEC’s low-power digital chip and processor architectures and implementation in advanced technology nodes. His current research interests include AI, machine learning and neuromorphic computing, computer architectures, design methodologies, design-technology co-optimization, reliability, variability and low power design.